RTL IP licensing
License LeoGreenAI RTL-class architectural IP to embed the LEO execution core family and companion blocks into your SoC or ASIC. IP is offered in two grades (below): one for hardening only without changing the microarchitecture, and one that provides RTL for architectural modification. Integrations can scale from single accelerators to multi-memory topologies.
Two license grades
Hardening only
Fixed microarchitecture — integration and signoff, not RTL editing.
- Use our compiler against an agreed, fixed LeoGreenAI configuration.
- No architectural changes to the RTL on your side.
- FPGA: Generated bitstream plus supporting collateral.
- ASIC: Path to netlist (or equivalent place-and-route handoff) from the locked architecture — not RTL meant for microarchitectural editing.
Architectural modification
RTL in hand — shape the architecture within your agreement.
- You receive RTL with rights to change the architecture: sizes, topology, blocks, and related parameters (per license scope).
- Supports deep co-design and node-specific tuning.
- Compiler and ISA alignment can be co-evolved with your modified RTL where the license permits.
Exact deliverables, review rights, and export terms are set in each agreement; the split above describes what class of artifact you work with in each grade.
Why teams license
- Time-to-silicon — drop-in accelerator subsystem with a known ISA and compiler story.
- Memory flexibility — DISK-style interfaces support parallel DRAM channels, unified or split traffic, and heterogeneous timing, with an interface philosophy oriented toward future extension.
- Extensibility — open-ended ISA and CSM extension philosophy for long product lifecycles.
- Observability — CSM for bring-up, field diagnostics, and partner-visible performance accounting.
Design intent
The LEO execution core and memory subsystem are designed for strong efficiency and inference throughput. The memory and host-attach interfaces emphasize extendability—additional channels, devices, and traffic classes as your program requires. Hardened IP deliverables are targeted toward best-in-class energy efficiency in their category.
LeoGreenAI does not publish headline efficiency, speed, or power numbers on the public website. We discuss configuration-specific behavior, benchmarks, and signoff evidence under NDA, using methodologies and on-chip visibility (including CSM) appropriate to your process node and workloads.
Typical deliverables (under agreement)
- Configurable LEO execution core and selected companion IPs (memory interface, host attach, attention support blocks, etc.).
- Integration guides, recommended verification hooks, and compiler alignment for your chosen configuration surface.
- Commercial terms scoped to use case: research, single product line, or broader architectural license.
We do not publish competitor comparison tables or headline efficiency / performance / power figures on the web; diligence happens under NDA with artifacts appropriate to your process node and integration risk.
